1. Field of the Invention
The present invention relates generally to digital video processing, and in particular, to a method of synchronizing a digital video signal when it is transmitted or received.
2. Description of the Related Art
In conventional digital data systems, data is transmitted/received in the form of a binary digital signal including an unmodulated clock signal. However, a timing skew may be created between the transmission and reception of the digital signal. Therefore, the digital data system must be able to recover data accurately by overcoming the timing skew. For this purpose, a clock recovery circuit is adopted and a PLL (Phase Locked Loop) is widely used for clock recovery.
The PLL is a circuit that automatically adjusts the phase of a locally generated signal to the phase of an input signal. The PLL controls an oscillator or a periodic signal generator so that it maintains a constant phase angle relative to a reference signal. It is used for coherent demodulation of digital modulated signals, coherent carrier tracking, threshold extension, bit synchronization, and symbol synchronization. Phase synchronization is implemented by an elastic store (ES) which is capable of independent input and output and absorbs the phase jitter of an input signal induced by delay variations and distortion on a transmission line, resulting in framing phase synchronization at a particular time point.
FIG. 1 is a block diagram of a typical PLL. The PLL is includes a phase/frequency detector 11, a loop filter 12, and a voltage controlled oscillator (VCO) 13. Clock extraction from the input data in the typical PLL will be described below with reference to FIG. 1.
Referring to FIG. 1, upon input of external data, the phase/frequency detector 11 extracts the clock component of the data, compares its phase with the phase of a signal received from the VCO 13, and provides the phase difference to the loop filter 12. The loop filter 12 filters the error signal received from the phase/frequency detector 11 and compensates a feedback loop so that the VCO 13 outputs a precisely phase-synchronized clock signal.
However, many networks encompass a myriad of data rates so that the general PLL in such networks is problematic. In order to recover data transmitted at such varying data rates, it is critical to recover a clock at each data rate. Therefore, in order to use a conventional PLL in a network encompassing a wide range of data rates, a plurality of PLL circuits that are respectively tuned to different data rates must be provided.
In this regard, the variable data rate situation, the clock recovery circuit configuration request a plurality of different VCOs (analog devices), resulting in increased complexity. Setting points are under analog control and thus they are sensitive, which makes precise phase synchronization challenging. Moreover, the clock recovery circuit is very difficult to implement except with use of a clock extracting device for existing data rates.
It is necessary to extract clock signals at different data rates in a broadcasting and communication environment. For example, digital video data is transferred at a data rate of 270 Mbps in DVB-ASI (Digital Video Broadcasting-Asynchronous Serial Interface) and at varying data rates of 10 to 80 Mbps in HDTV (High Definition Television). In the conventional technology involving the PLL, the clock extraction at the variable data rate requires hardware replacement or addition for each different data rate.
Accordingly, there is a need in the art for improved clock recovery mechanisms.